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Blocked all-pairs shortest paths algorithm on Intel Xeon Phi KNL processor : a case study

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Rucci, Enzo

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Material type: Article

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Summary: Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound ap- plications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.

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Item type	Home library	Collection	Call number	URL	Status	Date due	Barcode
Capítulo de libro	Biblioteca de la Facultad de Informática	Biblioteca digital	A0926 (Browse shelf(Opens below))	Link to resource	No corresponde

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Previous	A0923 Analysis of methodologies of digital data collection in web servers	A0924 Analysis of RAPL energy prediction accuracy in a matrix multiplication application on shared memory	A0925 Beyond the GUI in agriculture : a bibliographic review, challenges and opportunities	A0926 Blocked all-pairs shortest paths algorithm on Intel Xeon Phi KNL processor : a case study	A0927 CAN bus experiments of real-time communications	A0928 Conflict management in the collaborative description of a domain language	A0929 Context-aware mobile applications : taxonomy of factors for building approaches	Next

Formato de archivo PDF. -- Este documento es producción intelectual de la Facultad de Informática - UNLP (Colección BIPA/Biblioteca)

Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound ap- plications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.

Congreso Argentino de Ciencias de la Computación (23ro : 2017 : La Plata, Argentina)